Abishek Budihal — Embedded Systems & Firmware Engineer

U2

About

I'm an Electronics & Communication Engineering graduate (VTU Belagavi, CGPA 8.0) who builds things at the boundary of hardware and software — the layer where a register write becomes a voltage on a pin.

My six months at DRDO NSTL were spent writing bare-metal firmware for ARM Cortex-M3 and AVR ATxmega targets: interrupt-driven UART/SPI/I2C drivers and navigation-communication protocol stacks, work that earned me a Letter of Recommendation from a Scientist-'B' there. Outside of that, I've designed and verified a custom AXI4-Lite peripheral in Verilog, and built a mixed-signal DAC system accurate to 0.037% of full scale.

I'm currently a Trainee AV Design Engineer at Online Instruments (India) Ltd, working AV system design end-to-end — but the pull toward embedded systems, firmware, and silicon-adjacent work is what got this site built in the first place.

CH1Embedded C / C++

CH2Verilog / SystemVerilog

CH3STM32 · ESP32 · AVR

CH4UART · SPI · I2C · CAN

U3

Experience

JUN 2026 — PRESENT

Trainee AV Design Engineer

Online Instruments (India) Ltd.

AV/VC system design for enterprise client projects — signal-chain design, BOQ consolidation, and internal technical training materials on AV protocols and encode/decode systems.

SEP 2025 — FEB 2026

Firmware Intern

DRDO — Naval Science & Technological Laboratory (NSTL)

Bare-metal firmware for ARM Cortex-M3 and AVR ATxmega128A1U: interrupt-driven UART / SPI / I2C drivers and navigation-communication protocol implementation. Received a Letter of Recommendation from Scientist-'E'.

EDUCATION

B.Tech, Electronics & Communication Engineering

VTU Belagavi — CGPA 7.8

Coursework and independent projects spanning digital electronics, computer architecture, signal processing, and FPGA/VLSI design.

U4

Projects

PrecisionDAC — Mixed-Signal Output System

Embedded CAVR ATxmega128A1U TI DAC81408SPIIEEE 754

Problem: Deliver a high-accuracy analog output from a floating-point setpoint over a resource-constrained AVR MCU.
Approach: Wrote Embedded C firmware to convert IEEE 754 floating-point values into the DAC81408's register format and drive it over SPI, with a serial link for setpoint updates.
Challenges: Getting bit-exact floating-point-to-register conversion right, and debugging the analog output path against expected values on a bench scope.
Result: 0.037% full-scale error, verified against reference measurements.

GitHub link →

AXI4-Lite DMA Controller & Slave Peripheral

VerilogSystemVerilog UVMVivadoRTL

Problem: Build a custom AXI4-Lite slave peripheral and DMA controller front-end from scratch, with proof it actually works.
Approach: Designed the RTL and register map in Verilog, then wrote a SystemVerilog UVM testbench to drive and check every register path.
Challenges: Reaching full functional coverage meant finding and closing edge cases in the handshake and address-decode logic, not just the happy path.
Result: 11/11 tests passing with 100% functional coverage in simulation.

GitHub link →

Personal Finance Dashboard

ReactNode.jsMongoDBAuth

Problem: Track personal expenses across categories without spreadsheets.
Approach: Built a full-stack app with a React dashboard, a Node.js/Express API, and MongoDB for storage, with user authentication.
Challenges: Modeling recurring vs. one-off expenses cleanly for accurate category-level dashboards.
Result: A working expense-tracking dashboard with authenticated user accounts.

GitHub link →

U5

Technical Skills

Embedded & Firmware

Embedded C

C++

Python

Hardware & HDL

Verilog / SystemVerilog

PCB Design (Altium)

Hardware Debugging

Protocols

UART / SPI / I2C

CAN / RS232

Ethernet

Tools

STM32CubeIDE / Keil

Vivado

Git / GitHub

U6

GitHub

—Repositories

—Stars

—Followers

Fetching live data from the GitHub API…

U6.1

Achievements

0.037%

Full-scale error on the PrecisionDAC mixed-signal system

11 / 11

UVM tests passing, 100% functional coverage on the AXI4-Lite core

7.8

CGPA, B.Tech ECE, VTU Belagavi

LOR

Letter of Recommendation from a Scientist-'E' at NSTL (DRDO)

U7

Contact

Open to embedded systems, firmware, and hardware-adjacent roles. The fastest way to reach me:

Email me LinkedIn GitHub

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